1. Technical Field
This disclosure relates to semiconductor devices and more particularly, to a self-aligned interconnect and method for forming the self-aligned interconnect.
2. Description of the Related Art
Semiconductor devices typically include several metal layers which includes metal lines. It is often required to connect metal lines between such layers. This is performed using vertical interconnects or vias between the metal layers. The following is a description of a typical process sequence used to fabricate vias on top of a conductor.
A conductive or metal layer is patterned and formed into metal lines, for instance, by lithographically masking areas to be protected from an etchant material. A dielectric layer is formed on the metal layer. Locations for vias are lithographically defined. For example, a resist layer is deposited and patterned by a photolithographic image. Depending on the resist used and the processes to be performed a negative resist mask or a positive resist mask may be used. The mask and resist are exposed to electromagnetic radiation, usually light, which develops the resist layer to allow etching of portions of the mask while other portions remain. The remaining portions protect the underlying surface partly such that etching a pattern into the dielectric layer may be performed. Vias may be formed in the etched areas to connect one metal layer to a different metal layer.
Reflections of the incident radiation from the embedded structures on the resist are usually considered undesirable due to the inhomogeneity across the surface of a given chip. The conventional approach is therefore to eliminate such reflections by providing anti-reflective coatings on the underlying surfaces.
In addition, the lithographic mask and the metal lines of the metal layer must be aligned so that when the etched areas in the dielectric for via formation are created, they coincide with metal lines in the metal layer below the dielectric layer. This is often difficult in particular with critical feature sizes below 0.5 microns.
To account for alignment variations (slight misalignments), a "landing pad" or metal line under the via is typically formed having a larger thickness. The larger thickness is usually larger than the via and is preferably the via diameter plus the worst case misalignment tolerated by a process specification for the device. The large landing pad consumes layout area for a chip design and therefore contributes to the factors that increase chip size.
Therefore, a need exists for a self-aligned interconnect and method for forming the self-aligned interconnect for providing reduced layout area during fabrication of semiconductor chips. A further need exists for a method of exposing resist by exploiting radiation reflections from layers having a greater reflectance.